The DRAM Architecture War: the 4F² Schism, China's Second Front, and Memory Sovereignty

Only the five events side by side reveal the picture:

① MU publicly abandons 4F² (10/21).At its tech symposium, CTO-tier comments called the rival 4F² vertical-transistor design "fundamentally problematic," committing to the current 6F² layout until a direct jump to 3D DRAM (NAND-style multi-layer stacking) in 2027. Wedbush framed it two days later as a "formal pivot." ② Samsung's CTO confirms 4F2 VCT development (SEDEX, 10/16-20 window).Song Jae-hyuk confirmed the work at the Seoul expo — with no production timetable — a group-level disagreement with MU's "fundamental problems" verdict. ③ CXMT's 12/31 hard deadline.The year-end 4F² server DDR5 RDIMM promise stands — the war's first falsifiable ruling. ④ YMTC reveals the second front (Counterpoint, 10/23).The pure-NAND maker has been producing 16Gb LPDDR5X (7,500 MT/s) at ~5k wpm at Fab 2 since October 2025, and is now preparing 9,600 MT/s at Fab 3 on VCT 4F² + Xtacking 4.0 hybrid bonding. ⑤ SK hynix scraps Solidigm's IPO (10/23) + the China-NAND map is redrawn.The former is "capacity sovereignty over securitization in a shortage"; the latter (Reuters exclusive chain) is Samsung's Xi'an "Monami" project converting to 286-layer V9 (5k→40k wpm by Dec 2027) and SKH's Dalian going beyond 240 layers — all gated on a single policy valve: BIS approval.

Compressed to one sentence: the unit of DRAM competition is shifting from "process node" to "cell architecture" — and Chinese players hold first-mover design-density chips on two fronts (server and mobile) simultaneously.

Chain 1: cell area → bit output → cost curve.4F²'s paper promise is a cell area roughly one-third smaller than 6F² — on the same 300mm wafer, the same DUV lithography, bit output steps up directly. That is the entire Chinese wager: substituting design density for process shrinks under an EUV embargo. MU's rebuttal is yield and thermals (vertical transistors' capacitor aspect ratio and heat paths are unsolved engineering); Samsung's endorsement says it believes the engineering is solvable. If 4F² works in CXMT/YMTC hands, 2028 conventional DRAM's marginal cost curve gains a new player group — not a linear "China share +5pts" extrapolation, but a change in the slope of the cost curve.

Chain 2: Xtacking/hybrid bonding → the 3D DRAM bridge.YMTC's Xtacking 4.0 manufactures the cell wafer and the peripheral-logic wafer separately, then hybrid-bonds them — NAND-era muscle that happens to be the prerequisite technology for 3D DRAM. Note the irony: MU's endgame (3D DRAM 2027) is the same as YMTC's — but YMTC transitions smoothly from 4F² while MU must leap from 6F². The real disagreement in this war is not direction; it is path and timing.

Chain 3: the HBM / conventional DRAM fork deepens.HBM side: 2027 capacity is already locked by LTAs (Samsung ~80%, MU ~75%, SKH five-year agreements), and the NVHBM base-die unification on TSMC 3nm (pending official confirmation at 10/28) further binds HBM's logic layer into the leading-edge ecosystem — HBM's moat is "qualification + packaging ecosystem," which 4F² cannot touch. Conventional side: open markets, spot pricing, no qualification wall — precisely the battlefield where 4F²'s cost advantage cashes in. The vague "memory is tight" narrative will split in 2027-28 into two independent cycles: structurally tight HBM and cyclically loose conventional bits.This week the market traded "memory" as one block, flattening the fork entirely.

Chain 4 (NAND side): sovereignty and authorized capacity.The substance of SKH scrapping Solidigm's IPO: Dalian's expansion (Solidigm's only NAND base, the 240-layer upgrade pending) no longer depends on carve-out financing — supply decisions move from "capital-market windows" back to "industrial judgment." Samsung/SKH upgrading China plants to 286/240 layers ("authorized-capacity maximization" within the VEF framework) is a defensive hedge against YMTC's share attack: offsetting incremental threat with authorized存量 capacity. NAND's war is therefore not architectural (3D NAND is already the norm) but geographic and licensed: every BIS approval or silence redraws the 2027 bit-growth curve.